Processes That Also Support SCMOS Rules

Processes offered by MOSIS that also support SCMOS rules.

MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules, which provide a nearly process- and metric-independent interface to many CMOS fabrication processes available through MOSIS.

Only some of the processes offered by MOSIS support the SCMOS vendor-independent, scalable rules layout rules.

Use SCMOS layers and rules for portability and simplicity. Use vendor specific rules for fine-tuned layout and for those processes that support only their native layers and rule set. Not all vendor layers are supported by SCMOS rules and layers.

If a technology is not listed, it is not supported by SCMOS rules.



Foundry Comparable Process1 Technology Code Layer Map
ON Semi 0.50 micron, 1P3M, C5 SCN3M, SCN3M_SUBM See SCN3M map

0.50 micron, 2P3M, C5 SCN3ME, SCN3ME_SUBM See SCN3ME map

1 MOSIS has not issued SCMOS design rules for some vendor-supported options. Most non-standard options (as, medium threshold voltage) are available only for projects designed using the vendor set of layers and rules.