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8HP SiGe BiCMOS Process
GF Semiconductor 0.13 Micron
Information vital to preparing and submitting a design for fabrication in this process has been posted to the MOSIS Secure Document Server.
All users must read the checking procedures and density requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read the GF policy described in "Checking and Error Disposition Strategy for GF Designs."
Process Description
MOSIS is offering access to the GF 0.13 micron SiGe 8HP technology for prototype and low volume fabrication. Leadfree C4 (GF's flip chip bumping) is subject to availability at additional cost. Advance notice required. Please submit your inquiry through the MOSIS Support System
Supported Metal Stack:
M1, M2, M3 M4, MQ, LY, AM
Supply voltage are 1.2/2.5 V core and 2.5 V I/O. Also available now is 3.3V I/O. The default stack is 7 metal layers - wirebond - (M1, M2, M3, M4, MQ, LY, AM) QY and/or QY/HY MiM. MOSIS supports 7LM DM (new option) and/or C4 designs when possible -- with sufficent advance notice to the MOSIS Support System
Please refer to the List of 8HP Supported Options page for the options available by default on MOSIS MPW runs in this technology.
Other configurations are available for dedicated runs, or on MPW runs by prior arrangement. Please contact MOSIS support for additional details, e.g. costs.
Design ConsiderationsTo ensure that submitted data is on a 10 nm grid, please stream-out at 1 DBU = 10 nm (Cadence 0.010, not 0.001). MOSIS does not fill for GF processes. Designs for GF runs must meet the GF fill requirements when submitted.
GF Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
GF has sub-licensed MOSIS to distribute this information to selected customers.
The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the GF SiGe Design Kits page are the only kits and files available.
Design rules supported by this technology
Only the GF design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for the 8HP process is GF_8HP.
Reticle/Wafer Size, Steps, Die and Wafer Thickness
| GF SiGe 0.13 Micron 8HP Process | ||||||||
|---|---|---|---|---|---|---|---|---|
|
Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) |
Die Thickness (+/- .5 mil) |
Bumped Die Thickness *
(+/- .5 mil) |
Wafer Thickness | |||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | |||
| 8 | 18 x 20 | 60 | 10 | 250 | 10 | 250 | 30 | 760 |
* Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.