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Information For IC Designers
A variety of design flows (digital, analog, mixed-signal) can be used with a number of different CAD tools, technology files, design kits, libraries and IP to create designs for processes accessed by MOSIS.
A list of links of pages on the MOSIS web site most commonly used for project design.
Design kits (PDKs), technology files, etc. (see design kit summary) that support a variety of CAD tools, e.g. Cadence, Mentor, and Synopsys. Except where noted, these are distributed free of charge and are made available (other than ams AG) through our document server after signature of the MOSIS customer agreement and the vendor required agreements.
IP (e.g. standard cells, IOs, memories, processor cores, etc.)
Standard cell libraries, I/Os (pads), and memory generators for various processes are available from ARM for commercial and academic organizations. Academic organizations should contact the ARM University Program.
MOSIS commercial customers can contact Aragio directly.
A variety of IP is available for MOSIS commercial customers via the Cadence IP program
A family of processor cores available from Imagination Technologies.
An open architecture processor core approach.
A variety of IP, e.g. standard cells and memories are available for MOSIS commercial and academic customers via the DesignWare IP program.
ChipEstimate.com is a resource for chip size estimation and available IP.
Additional IP is available through MOSIS