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Information For IC Designers
A variety of design flows (digital, analog, mixed-signal) can be used with a number of different CAD tools, technology files, design kits, libraries and IP to create designs for processes accessed by MOSIS.
Design kits (PDKs), technology files, etc. (see design kit summary) that support a variety of CAD tools, e.g. Cadence, Mentor, Synopsys and Tanner. Except where noted, these are distributed free of charge and are made available (other than austriamicrosystems) through our document server after signature of the MOSIS customer agreement and the vendor required agreements.
Vendor design rules, SPICE models, etc. are available for each process. MOSIS provides electrical test data and SPICE parameters from MOSIS measurements on most MPW (multiproject wafer) runs. Projects submitted to MOSIS for fabrication can be designed using either the vendor's native design rules (specific to a process) or (for some processes) the SCMOS vendor-independent, scalable rules. These rule sets cannot be mixed within a design. SCMOS kits, cells and technology files are available.
Standard Cells, IP
Standard cell libraries enabling synthesis to place and route design flows are available for selected processes.
MOSIS commercial customers can contact Aragio directly.
A variety of IP, e.g. standard cells and memories are available for MOSIS commercial and academic customers via the DesignWare IP program.
ChipEstimate.com is a resource for chip size estimation and available IP.
Additional IP is available through MOSIS