Information For IC Designers

A variety of design flows (digital, analog, mixed-signal) can be used with a number of different CAD tools, technology files, design kits, libraries and IP to create designs for processes accessed by MOSIS.

Design Kits and Rules

Design kits (PDKs), technology files, etc. (see design kit summary) that support a variety of CAD tools, e.g. Cadence, Mentor, and Synopsys. Except where noted, these are distributed free of charge and are made available (other than ams AG) through our document server after signature of the MOSIS customer agreement and the vendor required agreements.

Technology Code and Layer Map

MOSIS uses technology codes so that a user can specify which set of layout rules (vendor or SCMOS) and which set of options has been used in a submitted layout file.

Layer maps define which layers are accepted, including which are required and which are optional for a technology code.

Globalfoundries / TSMC / ams / ON Semiconductor


Tool Organization or Company
BSIM3 (SPICE 3f5) University of California at Berkeley
Hspice Synopsys
PSpice Cadence-Orcad
Virtuoso Spectre MMSIM Cadence
SmartSpice Silvaco (formerly Simucad)
T-Spice Tanner

IP (e.g. standard cells, IOs, memories, processor cores, etc.)


Standard cell libraries, I/Os (pads), and memory generators for various processes are available from ARM for commercial and academic organizations. Academic organizations should contact the ARM University Program.



MOSIS commercial customers can contact Aragio directly.


A variety of IP is available for MOSIS commercial customers via the Cadence IP program


A family of processor cores available from MIPS.


An open architecture processor core approach.


A variety of IP, e.g. standard cells and memories are available for MOSIS commercial and academic customers via the DesignWare IP program. is a resource for chip size estimation and available IP.

Submitting a Design

How to Submit/Update A Design To MOSIS